Defect Based Testing of Superconductor Electronics

Recent advances in computing and telecommunication technologies require ultra-highspeed and high-precision devices in the digital domain for their realization. The clock frequencies of semiconductor devices have increased beyond expectations, but will not be able to solve the above-mentioned problems in the near future. At this point, superconductor electronics (SCE) technology is a promising candidate as the theoretical limits are around one Terahertz. The fastest digital device built in this technology, a 770 GHz Toggle flip-flop, proves that SCE is capable of overcoming the challenges. Much work has been done in the recent years with regard to the development of devices and systems in SCE. But little is known about the defects and fault mechanisms occurring in this technology. This is, however, of crucial importance in realizing the required complexity of systems. In this paper we present an approach for extracting the information of defects in the process. For this purpose, a set of test structures has been designed for the European SCE foundry, and associated measurement procedures have been developed. These (measured) defects are subsequently translated into fault models and a fault list by using Inductive Fault Analysis (IFA). In the paper we present the details of one of the most probable defects and its influence on circuits, in our case a delta ADC. Finally we show by simulations how BIST can be used to detect such a fault at system level.